Explore the machine

Tap a package or card to focus. This example is a conventional desktop with a discrete GPU, not an integrated or unified-memory system. Pinch or scroll to zoom at your fingers or cursor; drag empty space to pan. Breadcrumbs, ← and Fit take you back.

Keyboard: Tab to a component. Enter or Space opens a leaf explanation or enters a parent. + / − zoom, arrow keys pan, Home fits the map, Escape closes an explanation first, then returns to the parent. ? opens this help. Traces have independent Play / Pause and Step controls. Follow frames the current signal. Pan, pinch, zoom or focus a block to turn following off; trace selection still opens the relevant region. Tap a circuit part to select it without moving the map. Double-click or double-tap the same part to open its explanation. On narrow screens, circuit focus keeps readable scale; drag across the parent to inspect the rest. Amber wires carry addresses, blue carries data (including instructions), and gray carries control.

Exactly three layers: packages and devices, mechanisms, functional circuit parts. CPU grouping labels add no layer. The software panel is outside the motherboard and is not a chip. Each trace is an independent scenario, not a shared global simulation. Displayed flags follow that scenario; merely changing the view does not reset them. Completion, eviction and replacement bookkeeping are abstracted. Address, data and control wires terminate at fixed named ports. Arrowheads and moving payloads show direction. Overview bundles show physical links: CPU DDR through motherboard traces and the DIMM socket, independent PCIe links to GPU and NVMe, and graphics-card local memory. PCIe is bidirectional packet transport. Deeper amber, blue and gray paths show logical transactions, not three universal physical PC buses. Traces show logical dependencies, not exact cycles; translation and cache work may overlap.

CPU topology and MOESI-style ownership are simplified. Functional circuits are illustrative, not literal netlists. ALU sum/carry branches, cache metadata and data paths are distinct. Junction dots join a net; unmarked crossings do not. The cache circuit shows one candidate way, with set indexing and replacement policy abstracted. The second-level TLB shares this core’s instruction/data translations, not all machine cores. Page-table entries physically reside in memory, even though the OS panel shows their management. The CPU package contains the system memory controller and PCIe root ports. The graphics card contains a PCIe endpoint, copy engine and its own VRAM controller. A mapped host-buffer DMA transfer traverses PCIe, the CPU fabric and DDR. CPU cores submit work but do not copy each byte. Pinning, DMA authorization, synchronization and IOMMU behavior are platform-dependent. CPU↔GPU cache coherence is not assumed. The x16 link is illustrative; channel counts, PCIe generation and bandwidth are abstracted. Toy instruction locations 100/101/102 do not imply real instruction byte lengths.

Physical topology: Intel integrated memory controller · Intel PCIe root ports · NVIDIA physical memories · Pinned memory and DMA.

References: Linux page tables · Linux TLB · NVIDIA cache granularity